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* [[Michael Valenti]], [[Zvonko Vranesic]] ('''1977'''). ''[http://portal.acm.org/citation.cfm?id=810241 Experiences with CHUTE]''. [[ACM]] conference
* [[Zvonko Vranesic]] ('''1977'''). ''Multiple-Valued Logic: An Introduction and Overview''. [[IEEE#TOC|IEEE Transactions on Computers]], Vol. 26, No. 12
* [https://dblp.uni-trier.de/pers/hd/h/Hamacher:V=_Carl Carl Hamacher], [[Zvonko Vranesic]], [https://www.linkedin.com/in/safwat-zaky-8a8a1139/ Safwat Zaky] ('''1978'''). ''Computer Organization''. [https://en.wikipedia.org/wiki/McGraw-Hill_Education McGraw-Hill]
==1980 ...==
* [https://en.wikipedia.org/wiki/Hussein_T._Mouftah Hussein T. Mouftah], [https://en.wikipedia.org/wiki/Kenneth_C._Smith Kenneth C. Smith], [[Zvonko Vranesic]] ('''1980'''). ''Ternary Rate-Multipliers''. [[IEEE#TOC|IEEE Transactions on Computers]], Vol. 29, No. 10
* [[Zeljko Zilic]], [[Zvonko Vranesic]] ('''1996'''). ''[https://www.computer.org/csdl/proceedings/fpga/1996/2576/00/25760024-abs.html Using BDDs to Design ULMs for FPGAs]''. [https://dblp.uni-trier.de/db/conf/fpga/fpga96.html FPGA 1996]
* [[Zvonko Vranesic]] ('''1998'''). ''[https://ieeexplore.ieee.org/document/679318/ The FPGA Challenge]''. [https://dblp.uni-trier.de/db/conf/ismvl/ismvl1998.html ISMVL 1998]
* [https://www.linkedin.com/in/ante-grbi%C4%87-0657665b/ Ante Grbić], [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [https://dblp.uni-trier.de/pers/hd/c/Caranci:S= Steve Caranci], [https://www.linkedin.com/in/robin-grindley-47550/ Robin Grindley], [https://dblp.uni-trier.de/pers/hd/g/Gusat:Mitchell Mitchell Gusat], [http://www.ece.ubc.ca/~lemieux/ Guy Lemieux], [https://dblp.uni-trier.de/pers/hd/l/Loveless:K= K. Loveless], [httpshttp://dblpmy.uni-trierece.queensu.deca/perspeople/hdN-Manjikian/m/Manjikian:Naraig index.html Naraig Manjikian], [https://www.linkedin.com/in/sinisasrbljic/ Sinisa Srbljic], [https://www.genealogy.math.ndsu.nodak.edu/id.php?id=67137 Michael Stumm], [[Zvonko Vranesic]], [[Zeljko Zilic]] ('''1998'''). ''[https://ieeexplore.ieee.org/document/724441/ Design and Implementation of the NUMAchine Multiprocessor]''. [https://dblp.uni-trier.de/db/conf/dac/dac98.html DAC 1998], [http://www.eecg.toronto.edu/parallel/parallel/docs/dac98.pdf pdf] <ref>[http://www.eecg.toronto.edu/parallel/parallel/numadocs.html Documentation on the NUMAchine Multiprocessor]</ref>
* [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [[Zvonko Vranesic]] ('''1999'''). ''[http://www.mhhe.com/engcs/electrical/brownvranesic/ Fundamentals of Digital Logic with VHDL Design]''. [http://catalogs.mhhe.com/mhhe/home.do McGraw-Hill]
==2000 ...==
* [https://www.linkedin.com/in/robin-grindley-47550/ Robin Grindley], [http://www.eecg.toronto.edu/~tsa/ Tarek Abdelrahman], [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [https://dblp.uni-trier.de/pers/hd/c/Caranci:S= Steve Caranci], [https://dblp.uni-trier.de/pers/hd/d/DeVries:D= D. DeVries], [https://www.genealogy.math.ndsu.nodak.edu/id.php?id=67177 Benjamin Gamsa], [https://www.linkedin.com/in/ante-grbi%C4%87-0657665b/ Ante Grbić], [https://dblp.uni-trier.de/pers/hd/g/Gusat:Mitchell Mitchell Gusat], [https://dblp.uni-trier.de/pers/hd/h/Ho:R= R. Ho], [https://www.genealogy.math.ndsu.nodak.edu/id.php?id=99397 Orran Krieger], [http://www.ece.ubc.ca/~lemieux/ Guy Lemieux], [https://dblp.uni-trier.de/pers/hd/l/Loveless:K= K. Loveless], [httpshttp://dblpmy.uni-trierece.queensu.deca/perspeople/hdN-Manjikian/m/Manjikian:Naraig index.html Naraig Manjikian], [https://dblp.uni-trier.de/pers/hd/m/McHardy:P= P. McHardy], [https://www.linkedin.com/in/sinisasrbljic/ Sinisa Srbljic], [https://www.genealogy.math.ndsu.nodak.edu/id.php?id=67137 Michael Stumm], [[Zvonko Vranesic]], [[Zeljko Zilic]] ('''2000'''). ''The NUMAchine Multiprocessor''. [https://dblp.uni-trier.de/db/conf/icpp/icpp2000.html ICPP 2000], [http://www.eecg.toronto.edu/parallel/parallel/docs/icpp00.pdf pdf]
* [[Valavan Manohararajah]], [https://www.linkedin.com/in/terry-borer-501847/ Terry P. Borer], [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [[Zvonko Vranesic]] ('''2002'''). ''[https://www.semanticscholar.org/paper/Automatic-Partitioning-for-Improved-Placement-and-Manohararajah-Borer/d53ad046c377bedc4caa2f80dfc32339f0bc3d6d Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices]''. [https://dblp.uni-trier.de/db/conf/fpl/fpl2002.html FPL 2002]
* [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [[Zvonko Vranesic]] ('''2003'''). ''[http://www.mhhe.com/engcs/electrical/brownvranesic/ Fundamentals of Digital Logic with Verilog Design]''. [http://catalogs.mhhe.com/mhhe/home.do McGraw-Hill]
* [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [[Zvonko Vranesic]] ('''2008'''). ''[http://www.mhhe.com/engcs/electrical/brownvranesic/ Fundamentals of Digital Logic with VHDL Design]''. [http://catalogs.mhhe.com/mhhe/home.do McGraw-Hill], 3rd edition, [https://www.amazon.com/Fundamentals-Digital-Logic-Design-CD-ROM/dp/0077221435/ref=dp_ob_title_bk amazon]
==2010 ...==
* [https://dblp.uni-trier.de/pers/hd/h/Hamacher:V=_Carl Carl Hamacher], [[Zvonko Vranesic]], [https://www.linkedin.com/in/safwat-zaky-8a8a1139/ Safwat Zaky], [http://my.ece.queensu.ca/people/N-Manjikian/index.html Naraig Manjikian] ('''2011'''). ''Computer Organization and Embedded Systems''. 6th edition, [https://en.wikipedia.org/wiki/McGraw-Hill_Education McGraw-Hill], [https://www.amazon.com/Computer-Organization-Professor-Electrical-Engineering/dp/0073380652 amazon]
* [https://dblp.uni-trier.de/pers/hd/p/Plavec:Franjo Franjo Plavec], [[Zvonko Vranesic]], [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown] ('''2013'''). ''[https://dl.acm.org/citation.cfm?id=2535932 Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAs]''. [https://dblp.uni-trier.de/db/journals/trets/trets6.html TRETS], Vol. 6, No. 4
