File:Full-adder logic diagram.svg
Size of this PNG preview of this SVG file: 400 × 180 pixels. Other resolutions: 320 × 144 pixels | 640 × 288 pixels | 800 × 360 pixels | 1,024 × 461 pixels | 1,280 × 576 pixels.
Original file (SVG file, nominally 400 × 180 pixels, file size: 32 KB)
Summary
| Description |
English: Circuit Diagram of a Full Adder. |
| Date | |
| Source | Own work |
| Author | Inductiveload |
Licensing
|
I, the copyright holder of this work, release this work into the public domain. This applies worldwide. In some countries this may not be legally possible; if so: I grant anyone the right to use this work for any purpose, without any conditions, unless such conditions are required by law. |
File history
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 14:30, 23 March 2014 | | 400 × 180 (32 KB) | Tibor89 | Reverted to version as of 12:26, 23 March 2014 |
File usage
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